Tutorials

Track 1 8:30 am - 10 am

Navigating the Complexities of Automotive SoC Functional Safety: Challenges, Trends & Opportunities

Speaker & Affiliation: Gulroz Singh, NXP Semiconductors

Abstract: Advancements in Semiconductor and Automotive industries are facilitating a disruptive transformation towards Connected, Electrified & Autonomous Vehicles. These modern vehicles are being realized by advanced multi-processor System-on-Chips (SoCs) that power safety critical applications like ADAS, Vehicle Safety Systems and Sensor fusion & Processing. These safety critical systems enforces stringent functional safety requirements on the SoCs to ensure overall vehicle system safety. In this tutorial, we examine the current challenges that the industry faces with regards to functional safety both from an SoC architecture and System Application perspective. We also discuss the emergence of new verification and safety analysis methodologies that are being used to enhance the safety of advanced SoCs. We finish our discussion by indicating some key opportunities in the Automotive SoC Safety domain that could push the envelope in the near future.

Track 1 10:30 am - 12 pm

Characterization Techniques for High-Performance Analog-to-Digital Converters 

Speaker & Affiliation: Doug Garrity, NXP Semiconductors

Abstract: Given that the ‘real world’ is analog, analog-to-digital converters (ADCs) will play an increasingly critical role in both emerging applications ranging from edge computing to 6G telecommunications and more traditional applications ranging from electricity metering to automotive radar. For any of these applications, it turns out that the better the performance of the ADC, the better (and more easy to implement) the new system applications become. However, as ADC performance improves, real (and not Figure of Merit (FoM) based) ADC performance becomes significantly more difficult and more expensive to verify and unless proper techniques and extreme attention to detail are carefully applied, the true performance of an ADC will be nearly impossible to determine. Using a 24-bit Analog Front End (AFE) as a demonstration vehicle, this tutorial will present best practices (from a test/characterization perspective) for IC design, basic lab set up and equipment, evaluation boards, and static and dynamic data analysis along with simulated and measured results and an extensive list of lessons learned.

Track 1 1:30 pm - 5 pm

To Innovate Circuits to Reinvent Microelectronics You Must Unlearn What You Have Been Mistaught

Speaker & Affiliation: Colin McAndrew, NXP Semiconductors

Abstract: So, you want to design a nifty new analog / RF circuit. You will: use the understanding of transistor small-signal behavior that you learned from textbooks; run corner simulations; look at simulation audits of VDS-VDSsat to ensure that all of your MOS transistors remain in saturation; and analyze drain current mismatch using the conventional relative (i.e., percentage) variation 100 * (ID2-ID1)/ID1.

Wrong; wrong; wrong; and wrong.

This tutorial will go through each of those four items (and more), and teach you what is “wrong” with the “conventional wisdom.”

We will cover these specific topics:

• the “modulated resistance” view of how MOS transistors work

• the 5 basic approaches to MOS transistor modeling (CMC standard models are based on 4 of these)

• MOS transistor capacitances: why what you were taught about small-signal models is wrong, how to understand MOS (and bipolar) transistor capacitances and conductances – why Cgd and Cdg are different and which is more important (hint: it’s not the Cgd presented in design textbooks)

• statistics

  • • basic types of variability in devices

    • why corner models do not work for analog

    • how to calculate % variation properly

    • how to estimate std dev robustly

    • how Monte Carlo-like simulation of mismatch is compromised by “spurious correlation” between statistical samples

    • why mean +/- std dev is not an appropriate way to calculate variability (the “3 sigma” fallacy)

• why SPICE operating point information (VDSsat, gm, capacitances, etc.) is imprecise

• a brief overview of layout dependent effects (LDEs)

• where to expect inaccuracies in SPICE models

Track 2 8:30 am - 10 am

Quantum Machine Learning Algorithms and Applications

Speakers & Affiliations: Glen Uehara and Andreas Spanias, School of ECEE, SenSIP Center, Arizona State University

Abstract: This tutorial will present the basic concepts of quantum computing algorithms with the emphasis on Machine Learning. The tutorial will start with the physics of quantum systems and cover basic concepts and properties including qubits, entanglement and qubit deciphering errors. We then begin focusing on quantum data and building blocks of computational operations, simulation, and implementation. The discussion covers the methodologies used to transform classical machine learning algorithms to actual quantum expressions. The presentation on modeling algorithms will cover a hybrid classical-quantum approach and quantum simulators. In the last part of the tutorial, we present QML applications in solar energy, imaging, and audio classification.

Track 2 10:30 am - 12 pm

Efficient and robust energy-management IC design for wirelessly powered devices

Speaker & Affiliation: Hyung-Min Lee, Associate Professor, School of Electrical Engineering, Korea University, South Korea

Abstract: There are various applications that utilize the wirelessly powered devices such as implantable medical devices (IMD), wireless sensors, wireless chargers, RFID tags, and IoT devices. These systems require not only high efficiency but also robust and adaptive operation depending on surrounding environments to reliably receive, convert, and store the wireless power to supply the devices. For example, IMD with neural recording, stimulating, and processing functions have been proven as effective therapies to alleviate neurological diseases or substitute sensory modalities, while requiring large energy for more efficacious treatments. Wireless power transmission across the skin through coupled coils can be a viable solution for providing wireless power to such IMDs, but the inductive link performance is limited due to size constraints of the implant and safety issues in the tissue. Thus, the wirelessly powered devices such as IMDs require more aggressive energy-management techniques to further improve the end-to-end energy efficiency while ensuring precise, safe, and effective functions. In this talk, I will present various techniques for energy-management IC design including wireless power/data transfer, power conversion, regulation, energy backup, closed-loop control, etc.

Track 2 1:30 pm - 5 pm

Fault-Tolerant Cell-Based DLL Design for Heterogeneous Clock Synchronization

Speaker & Affiliation: Shi-Yu Huang, National Tsing Hua University, Taiwan

Abstract: When we design an SoC, or a multi-die IC consisting of 3rd-party IPs, heterogeneous components, or functional dice, synchronization of the clock signals across some of the components could be a headache. Fortunately, Delay-Locked Loop (DLL) comes to the rescue. However, a DLL is traditionally built with some analog circuitry inside and thus making the design process complicated if not mysterious for system integrators. The emergence of a cell-based DLL design style over the past two decades has alleviated this problem greatly. A cell-based DLL design is not only small but also robust to the process and temperature variation. Also, it could lend itself to automation as a DLL compiler and so one can generate a DLL instance at the push of a button. In this tutorial, we will take on a step-by-step journey to illustrate how you can make your own robust and testable fault-tolerant DLL easily using only standard cells. In the first part, specific topics for the design of a basic DLL such as phase detector, tunable delay line, phase-locking procedure, the coping strategy for process and temperature variation, and duty-cycle monitoring and correction will be covered in detail. In the second part, Fault and soft-Error Tolerant (FET) DLL architecture, featuring static timing correction and dynamic timing correction schemes to make Triple-Module-Redundancy (TMR) feasible in achieving pleasing performance in terms of the maximum phase error. Finally, we will touch upon the online DLL monitoring schemes which are often necessary to make a FET DLL truly trustworthy throughout its entire lifecycle.

Track 3 8:30 am - 12 pm

Open Source Design: From RTL to Silicon

Speakers & Affiliations: Mohamed Kassem and Tim Edwards, eFabless

Abstract: In recent years, the open-source community has made significant strides in enabling open-source ASIC design and fabrication, providing access to essential Electronic Design Automation (EDA) tools, Process Design Kits (PDK), and low-cost fabrication shuttle programs. 

This tutorial is for anyone who wants to get a design idea to silicon, whether a software or hardware person, experienced chip designer or novice; professional, student, or enthusiastic Maker. Efabless will demonstrate our ChipIgnite design flow that uses open source tools from RTL to GDS, open source PDKs for real foundry processes at 130nm or 180nm nodes, and the ready-made chip framework called Caravel that provides a padframe, a RISC-V processor for embedded testing and control of your project. 

This tutorial is an excellent opportunity for VLSI enthusiasts to expand their knowledge and expertise in open-source ASIC design, paving the way for creating cutting-edge, cost-effective chips. Join us, bring a laptop, and Efabless will provide a virtual server preinstalled with software and PDK data, and guide you through the steps from idea to tapeout.