Track 1


Navigating the Complexities of Automotive SoC Functional Safety: Challenges, Trends & Opportunities (Gulroz Singh; NXP Semiconductors)


Characterization Techniques for High-Performance Analog-to-Digital Converters (Doug Garrity; NXP Semiconductors)


To Innovate Circuits to Reinvent Microelectronics You Must Unlearn What You Have Been Mistaught (Colin McAndrew; NXP Semiconductors)

Track 2


Quantum Machine Learning Algorithms and Applications (Glen Uehara & Andreas Spanias; SenSIP Center, ASU)

Energy-management IC Design for Wirelessly Powered Devices (Hyung-Min Lee; Korea University)


Fault-Tolerant Cell-Based DLL Design for Heterogeneous Clock Synchronization (Shi-Yu Huang; National Tsing Hua University, Taiwan)

Track 3


Open Source Design: From RTL to Silicon (Mohamed Kassem & Tim Edwards, eFabless)

Track 1 8:30 am - 10 am

Navigating the Complexities of Automotive SoC Functional Safety: Challenges, Trends & Opportunities

Speaker & Affiliation: Gulroz Singh, NXP Semiconductors

Abstract: Advancements in Semiconductor and Automotive industries are facilitating a disruptive transformation towards Connected, Electrified & Autonomous Vehicles. These modern vehicles are being realized by advanced multi-processor System-on-Chips (SoCs) that power safety critical applications like ADAS, Vehicle Safety Systems and Sensor fusion & Processing. These safety critical systems enforces stringent functional safety requirements on the SoCs to ensure overall vehicle system safety. In this tutorial, we examine the current challenges that the industry faces with regards to functional safety both from an SoC architecture and System Application perspective. We also discuss the emergence of new verification and safety analysis methodologies that are being used to enhance the safety of advanced SoCs. We finish our discussion by indicating some key opportunities in the Automotive SoC Safety domain that could push the envelope in the near future.

Gulroz Singh is a Sr. Functional Safety Architect at NXP Semiconductors USA in the MCU/ MPU Engineering Department. Gulroz received his Master’s degree in Computer Engineering focused on Digital VLSI Design & Verification from Portland State University, OR, USA (2018). He has 5 years of experience developing functionally safe automotive products and has worked and consulted a number of Automotive tier suppliers and OEMs as a leading expert on functional safety. He is also a frequent speaker in technical conferences on safety and has contributed to technical articles in magazines around the world.

Track 1 10:30 am - 12 pm

Characterization Techniques for High-Performance Analog-to-Digital Converters 

Speaker & Affiliation: Doug Garrity, NXP Semiconductors

Abstract: Given that the ‘real world’ is analog, analog-to-digital converters (ADCs) will play an increasingly critical role in both emerging applications ranging from edge computing to 6G telecommunications and more traditional applications ranging from electricity metering to automotive radar. For any of these applications, it turns out that the better the performance of the ADC, the better (and more easy to implement) the new system applications become. However, as ADC performance improves, real (and not Figure of Merit (FoM) based) ADC performance becomes significantly more difficult and more expensive to verify and unless proper techniques and extreme attention to detail are carefully applied, the true performance of an ADC will be nearly impossible to determine. Using a 24-bit Analog Front End (AFE) as a demonstration vehicle, this tutorial will present best practices (from a test/characterization perspective) for IC design, basic lab set up and equipment, evaluation boards, and static and dynamic data analysis along with simulated and measured results and an extensive list of lessons learned.

Doug Garrity (S’85-M’86-SM’04-Fellow’11) received the B.S. degree from Portland State University, Portland OR, the M.S. degree from the University of Idaho, Moscow, ID, and the Ph.D. degree from Arizona State University, Tempe, AZ all in electrical engineering. He joined Motorola/Freescale/NXP in 1992 and is currently a Fellow of the Technical Staff at NXP, Chandler, AZ, where he is involved in the research and development of high-performance data converters for embedded applications. Dr. Garrity also teaches the graduate-level Nyquist-rate and Delta-Sigma analog-to-digital converter design classes at Arizona State University. He has received 49 U.S. Patents with several more pending in the field of data converter and analog VLSI circuits. 

Dr. Garrity became an NXP Fellow in 2015, was named a  Freescale Fellow in 2010 and received Freescale’s Master Innovator Award in 2009. He was a recipient of Motorola’s Distinguished Innovator Award, and was named a Motorola Dan Noble Fellow in 2003. Dr. Garrity also served as a member of the Technical Program Committee of the IEEE Custom Integrated Circuits Conference from 1994 through 2004. He also received the Semiconductor Research Corporation Mahboob Khan Outstanding Industry Liaison Award in 2001 and 2013. Dr. Garrity served as the chairman of the IEEE Kirchhoff Award committee in 2018 and 2019 and also served as the chairman of the SSCS Fellow Evaluation committee and has twice served as a guest editor for special issues of the IEEE Journal of Solid-State Circuits and served as an Associate Editor from 2002 to 2005. He has also served as an Associate Editor for the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 

Track 1 1:30 pm - 5 pm

To Innovate Circuits to Reinvent Microelectronics You Must Unlearn What You Have Been Mistaught

Speaker & Affiliation: Colin McAndrew, NXP Semiconductors

Abstract: So, you want to design a nifty new analog / RF circuit. You will: use the understanding of transistor small-signal behavior that you learned from textbooks; run corner simulations; look at simulation audits of VDS-VDSsat to ensure that all of your MOS transistors remain in saturation; and analyze drain current mismatch using the conventional relative (i.e., percentage) variation 100 * (ID2-ID1)/ID1.

Wrong; wrong; wrong; and wrong.

This tutorial will go through each of those four items (and more), and teach you what is “wrong” with the “conventional wisdom.”

We will cover these specific topics:

Colin McAndrew received the Ph.D. degree in systems design engineering from the University of Waterloo, Canada. He was at AT&T Bell Laboratories for 7 years, and since 1995 has been with NXP in Arizona, where he is a Fellow of Technical Staff. He is a Fellow of the IEEE, was an editor of the IEEE Transactions on Electron Devices from 2001 to 2010 and an editor of the IEEE Journal of the Electron Devices Society from 2013 to 2022. He is or has been on the technical program committees for the IEEE BCTM, ICMTS, CICC, and BMAS conferences. He received best paper awards from ICMTS in 1993 and 2012, CICC in 2002, and BCTM in 2015. He has published more than 130 refereed journal and conference papers, 10 book chapters, and one book, and given numerous invited papers and short courses at leading industry conferences. His works is primarily on compact and statistical modeling of semiconductor devices. 

Track 2 8:30 am - 10 am

Quantum Machine Learning Algorithms and Applications

Speakers & Affiliations: Glen Uehara and Andreas Spanias, School of ECEE, SenSIP Center, Arizona State University

Abstract: This tutorial will present the basic concepts of quantum computing algorithms with the emphasis on Machine Learning. The tutorial will start with the physics of quantum systems and cover basic concepts and properties including qubits, entanglement and qubit deciphering errors. We then begin focusing on quantum data and building blocks of computational operations, simulation, and implementation. The discussion covers the methodologies used to transform classical machine learning algorithms to actual quantum expressions. The presentation on modeling algorithms will cover a hybrid classical-quantum approach and quantum simulators. In the last part of the tutorial, we present QML applications in solar energy, imaging, and audio classification.

Glen Uehara has a BS and MSE in Electrical Engineering, from University of Hawaii and Arizona State University, respectively. He has been working as a communication and signal processing engineering in both commercial and defense industry.He is currently, Ph.D. student at the SenSIP lab in the School of Electrical, Computer and Energy Engineering at ASU, specializing in Quantum Information Algorithms specifically for Signal & Information Processing and Machine Learning. He is also currently working in the Quantum Laboratory at General Dynamics.  He is a Senior Member of IEEE and he has several IEEE conference publications with the most recent in quantum systems.

Andreas Spanias is Professor in the School of Electrical, Computer, and Energy Engineering at Arizona State University (ASU). He is also the director of the Sensor Signal and Information Processing  (SenSIP) center and the founder of the SenSIP industry consortium (also an NSF I/UCRC site). His research interests are in the areas of adaptive signal processing, speech processing, quantum machine learning and sensor systems. He and his student team developed the computer simulation software Java-DSP and its award-winning iPhone/iPad and Android versions. He is author of two textbooks: Audio Processing and Coding by Wiley and DSP; An Interactive Approach (2nd Ed.).  He contributed to more than 350 papers, 11  monographs, 19 full patents, 10 provisional patents and several IP pre-disclosures.  He served as Associate Editor of the IEEE Transactions on Signal Processing and as General Co-chair of IEEE ICASSP-99. He also served as the IEEE Signal Processing Vice-President for Conferences. Andreas Spanias is co-recipient of the 2002 IEEE Donald G. Fink paper prize award and was elected Fellow of the IEEE in 2003. He served as Distinguished Lecturer for the IEEE Signal processing society in 2004. He is a series editor for the Morgan and Claypool lecture series on algorithms and software.  He received the 2018 IEEE Phoenix Chapter award with citation:  “For significant innovations and patents in signal processing for sensor systems.”  He also received the 2018 IEEE Region 6 Outstanding Educator Award (across 12 states) with citation: “For outstanding research and education contributions in signal processing.”  He was elected recently to Senior Member of the National Academy of Inventors (NAI).

Track 2 10:30 am - 12 pm

Efficient and robust energy-management IC design for wirelessly powered devices

Speaker & Affiliation: Hyung-Min Lee, Associate Professor, School of Electrical Engineering, Korea University, South Korea

Abstract: There are various applications that utilize the wirelessly powered devices such as implantable medical devices (IMD), wireless sensors, wireless chargers, RFID tags, and IoT devices. These systems require not only high efficiency but also robust and adaptive operation depending on surrounding environments to reliably receive, convert, and store the wireless power to supply the devices. For example, IMD with neural recording, stimulating, and processing functions have been proven as effective therapies to alleviate neurological diseases or substitute sensory modalities, while requiring large energy for more efficacious treatments. Wireless power transmission across the skin through coupled coils can be a viable solution for providing wireless power to such IMDs, but the inductive link performance is limited due to size constraints of the implant and safety issues in the tissue. Thus, the wirelessly powered devices such as IMDs require more aggressive energy-management techniques to further improve the end-to-end energy efficiency while ensuring precise, safe, and effective functions. In this talk, I will present various techniques for energy-management IC design including wireless power/data transfer, power conversion, regulation, energy backup, closed-loop control, etc.

Hyung-Min Lee received the B.S. degree in electrical engineering from Korea University, Seoul, South Korea, in 2006, the M.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2008, and the Ph.D. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2014.

From 2014 to 2015, he was with the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA, as a post-doctoral researcher. From 2015 to 2017, he was with the IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, as a research staff member. In 2017, he joined the School of Electrical Engineering, Korea University, where he is currently an Associate Professor. His research interests include analog/mixed-signal IC and microsystem design for biomedical, sensor, power management, and IoT applications.

Prof. Lee has authored more than 70 peer-reviewed journals and proceeding papers regarding the IC design for energy-efficient systems and power management circuits. Prof. Lee was a recipient of the Silver Prizes in the 16th and 18th Human-Tech Thesis Prize Contest from Samsung Electronics, South Korea, in 2010 and 2012, respectively, and the Commendation Award in the 4th Outstanding Student Research Award from TSMC, Taiwan, in 2010. Also, he was a co-recipient of the Best Design Award from Asia and South Pacific Design Automation Conference (ASP-DAC) in 2018 and the Outstanding Student Paper Award from IEEE Custom Integrated Circuits Conference (CICC) in 2023. He currently serves as an Associate Editor for IEEE Open Journal of Circuits and Systems (OJCAS).

Track 2 1:30 pm - 5 pm

Fault-Tolerant Cell-Based DLL Design for Heterogeneous Clock Synchronization

Speaker & Affiliation: Shi-Yu Huang, National Tsing Hua University, Taiwan

Abstract: When we design an SoC, or a multi-die IC consisting of 3rd-party IPs, heterogeneous components, or functional dice, synchronization of the clock signals across some of the components could be a headache. Fortunately, Delay-Locked Loop (DLL) comes to the rescue. However, a DLL is traditionally built with some analog circuitry inside and thus making the design process complicated if not mysterious for system integrators. The emergence of a cell-based DLL design style over the past two decades has alleviated this problem greatly. A cell-based DLL design is not only small but also robust to the process and temperature variation. Also, it could lend itself to automation as a DLL compiler and so one can generate a DLL instance at the push of a button. In this tutorial, we will take on a step-by-step journey to illustrate how you can make your own robust and testable fault-tolerant DLL easily using only standard cells. In the first part, specific topics for the design of a basic DLL such as phase detector, tunable delay line, phase-locking procedure, the coping strategy for process and temperature variation, and duty-cycle monitoring and correction will be covered in detail. In the second part, Fault and soft-Error Tolerant (FET) DLL architecture, featuring static timing correction and dynamic timing correction schemes to make Triple-Module-Redundancy (TMR) feasible in achieving pleasing performance in terms of the maximum phase error. Finally, we will touch upon the online DLL monitoring schemes which are often necessary to make a FET DLL truly trustworthy throughout its entire lifecycle.

Shi-Yu Huang received his Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara, in 1997. Since 1999, he has joined the faculty of the EE Dept., National Tsing Hua University, Taiwan, until now. His recent research is concentrated on all-digital timing circuit designs, such as an all-digital phase-locked loop (PLL), an all-digital delay-locked loop (DLL), a time-to-digital converter (TDC), and their applications to parametric fault testing and reliability enhancement for 3D-ICs. He has published more than 170 technical papers (including 50 IEEE periodical papers). Dr. Huang ever co-founded a company in 2007-2012, TinnoTek Inc., specializing in a cell-based PLL compiler and system-level power estimation tools. He is a recipient of the best-presentation award or best-paper award 5 times, and a senior member of IEEE.

Track 3 8:30 am - 12 pm

Open Source Design: From RTL to Silicon

Speakers & Affiliations: Mohamed Kassem and Tim Edwards, eFabless

Abstract: In recent years, the open-source community has made significant strides in enabling open-source ASIC design and fabrication, providing access to essential Electronic Design Automation (EDA) tools, Process Design Kits (PDK), and low-cost fabrication shuttle programs. 

This tutorial is for anyone who wants to get a design idea to silicon, whether a software or hardware person, experienced chip designer or novice; professional, student, or enthusiastic Maker. Efabless will demonstrate our ChipIgnite design flow that uses open source tools from RTL to GDS, open source PDKs for real foundry processes at 130nm or 180nm nodes, and the ready-made chip framework called Caravel that provides a padframe, a RISC-V processor for embedded testing and control of your project. 

This tutorial is an excellent opportunity for VLSI enthusiasts to expand their knowledge and expertise in open-source ASIC design, paving the way for creating cutting-edge, cost-effective chips. Join us, bring a laptop, and Efabless will provide a virtual server preinstalled with software and PDK data, and guide you through the steps from idea to tapeout.

Mohamed Kassem is the CTO and Co-Founder of efabless.com, the first semiconductor company applying open community innovation to all aspects of product development. Prior to launching efabless in 2014, Mohamed held several technical and global leadership positions within Texas Instruments’ Wireless Business Unit. Mohamed led the first development of 45nm, 28nm analog & mixed-signal IP functions for wireless applications processors. Mohamed holds a Masters degree in Electrical Engineering from the University of Waterloo, Ontario, Canada. 

Tim Edwards is the Senior Vice President of Analog and Design at efabless.com, the first semiconductor company applying open community innovation to all aspects of product development. Prior to joining eFabless in 2016, Tim held several senior technical positions with the Johns Hopkins University Applied Physics Lab, MultiGiG, Ltd., and Analog Devices (after they acquired MultiGiG). Tim holds an MS in Electrical Engineering from Stanford and a PhD in Electrical and Computer Engineering from The Johns Hopkins University.