Prenote & Keynotes

Virtual Prenote
Wed July 26 1-2 pm ET

Speaker: Dr. Laurie Locascio
Under Secretary of Commerce for Standards and Technology & Director of the National Institute of Standards and Technology (NIST) 

Title: When the Government Makes Big Bets on Science and Technology: the CHIPS Act

Slides and recording coming soon ...

Bio for Laurie Locascio

Dr. Laurie Locascio is currently the Under Secretary of Commerce for Standards and Technology and the director of the National Institute of Standards and Technology (NIST). Locascio most recently served as vice president for research at the University of Maryland College Park and University of Maryland Baltimore.  She also served as a professor in the Fischell Department of Bioengineering at the A. James Clark School of Engineering with a secondary appointment in the Department of Pharmacology in the School of Medicine.

Before joining the University of Maryland, Locascio worked at NIST for 31 years, rising from a research biomedical engineer to eventually leading the agency’s Material Measurement Laboratory. She also served as the acting associate director for laboratory programs, the No. 2 position at NIST, providing direction and operational guidance for NIST’s lab research programs.

As a researcher, she has published 115 scientific papers and has received 12 patents in the fields of bioengineering and analytical chemistry. She is a fellow of the National Academy of Inventors, the American Association for the Advancement of Science, the American Chemical Society, and the American Institute for Medical and Biological Engineering.  Dr. Locascio was recently elected to the National Academy of Engineering.

Mon Aug 7 9:30-10:30 am AZ

Speaker: Dr. Ravi Mahajan
Intel Fellow, Assembly and Packaging Technology Pathfinding, Intel Corporation

Title: Directions, Challenges and Opportunities in Heterogeneous Integration 


Heterogeneous Integration (HI) is a powerful and crucial enabler for the continued growth of computing and communication performance.  Advanced packaging technologies are critical enablers of HI because of their importance as compact, power efficient platforms. This talk will focus on the tremendous opportunities in different application environments and focus on the projected evolution of advanced packaging architectures.  Interest in HI research has picked up in recent years and this opens up greater collaboration opportunities between academia and industry.  Specific examples, showing how product implementations take advantage of currently available HI technologies, to provide an unprecedented level of performance, will be used to describe the challenges and opportunities in developing robust, next generation advanced package architectures. A broad scope roadmap of the future generated as part of an industry-academic collaboration will be discussed in this context to highlight the opportunities generated by HI.  Intel’s engagement with federal programs in developing State-of-the-Art packaging solutions using Advanced Packaging technologies will also be described.   

Bio for Ravi Majahan

Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes including 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi joined Intel in 1992 after earning his Ph.D. in Mechanical Engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE.  He was elected to the National Academy of Engineering in 2022 for contributions to advanced microelectronics packaging architectures and their thermal management. 

Tues Aug 8 9:30-10:30 am AZ

Speaker: Dr. Larry Nagel, Omega Enterprises Consulting

Title: Fifty Years of SPICE


Exactly fifty years ago. Professor Donald O. Pederson and I presented a paper entitled "Simulation Program with Integrated Circuit Emphasis (SPICE)" at the IEEE 16th Midwest Symposium on Circuit Theory, as this conference was called then. This was the first paper on SPICE to be presented in public, although we had been working on SPICE at the University of California, Berkeley since 1971 and SPICE itself evolved from the CANCER class project taught by Professor Ronald A. Rohrer in the 1969-1970 school year at the University of California, Berkeley. Engineers entering the integrated circuit industry today weren’t even born when I released the first version of SPICE, but a vast majority of engineers have to learn SPICE to earn their degree! In this talk, I will chart the journey of SPICE, starting as a teaching program at the University of California, Berkeley, and spreading into industry and launching a cottage industry of software houses writing and supporting “alphabet SPICE.” I also give credit to the early principals in this journey, and share some amusing experiences. No one can say for sure, but I will speculate on how this particular program has evolved and yet stayed pretty much the same for more than fifty years. I can think of no other computer program that can make that claim.

Bio for Larry Nagel

Laurence W. Nagel is an independent consultant in the San Francisco Bay Area. He has worked in the integrated circuit industry for more than 50 years. While earning his BS, MS, and PhD degrees at the University of California, he developed the SPICE circuit simulation program which launched a cottage industry of SPICE simulation tools. Mr. Nagel then began a 20 year career at Bell Laboratories which included developing the ADVICE circuit simulation program; participating in the development of the Kull-Nagel bipolar model; designing analog circuits for submicron NMOS processes; working in the AT&T Intellectual Property Division on assertion of patents and negotiation of patent licenses; and serving as project manager in the development of the Celerity circuit simulation program. Mr. Nagel then joined Anadigics, Inc., where he managed simulation of RF integrated circuits; modeling and characterization of GaAs MESFET device processes; and importing silicon CMOS design tools and foundry support. In 1998, Mr. Nagel founded his own company, Omega Enterprises, to consult on analog circuit design, circuit simulation, semiconductor device modeling, and as an expert witness in patent litigation and trade secret misappropriation matters. In 2008, he returned to his native California where he now resides with his wife Jean in Kensington and operates his consulting company Omega Enterprises Consulting.

Wed Aug 9 9:30-10:30 am AZ

Speaker: Mr. Pierre Piel
Vice President and General Manager Radio Power, NXP Semiconductors

Title: Toward a Converged 6G Vision


The vision of a 6G future embodies a truly transformative, paradigm shifting technology. A connected 6G world stands to become purposeful through joint communication and sensing, addressing societal challenges not previously thought possible. Enabled by massive increases in available spectrum complimented by a move to distributed computing, 6G layers in altruistic aims such as closing the digital divide, enhancing safety and privacy, while striving to be truly sustainable. Foundational RF semiconductor technologies must be thoughtfully considered across ecosystem partners and investments carefully placed to minimize the component readiness gap to make this vision a reality. 

Bio for Pierre Piel

Pierre Piel is vice president and general manager of the Radio Power product line at NXP Semiconductors. He has more than 25 years of semiconductor industry experience and has held different roles in the development, launch and manufacturing of leading-edge radio frequency products.

He has a Master of Science degree in electrical engineering from the National Polytechnic Institute in Grenoble and Arizona State University. He lives in Scottsdale, AZ with his two kids and wife. He enjoys mountain bike riding, running and enjoys watching French soccer with his son.