Celebrating 50 Years of SPICE! 1973-2023

MWSCAS CHIPS Workshop

Workshop Co-Chairs: Todd Hylton (UCSD) and Antonio de la Serna (Siemens)

National investment from the US CHIPS+Science Act is poised to transform and reinvigorate the field of microelectronics in the US. However, there is still much uncertainty in how the Research funds will be allocated by NIST and DoD.

This workshop will bring together stakeholders including representatives from NIST, DARPA, IMEC, NSF, microelectronics / semiconductor / packaging industries, and academia for a workshop focused on the CHIPS Act. Our goal is to provide clarity and networking to foster collaborative discussions to help members of the CAS community understand upcoming opportunities, network with leaders in the field, and develop vision for how they can leverage those opportunities collaboratively. The workshop will include information sessions, panel discussions, and time for networking.

Workshop Goals: The goals of this workshop are to provide information about opportunities associated with the CHIPS+Science Act, to foster collaborative discussions and networking among representatives from government, industry, and academia, and to help members of the CASS community to build collaborative networks and pursue research opportunities related to the CHIPS Act. The workshop will include information sessions, panel discussions, and time for networking.

Agenda: (see below for speaker bios)

1:30-2:15 Keynote: CHIPS Act Information and Opportunities
Alex Liddle (NIST)

2:15-3:00 Vision for the US CHIPS Act. Why do we need this?
Panelists: Michael Fritze (Potomac Institute), Matt Kay (Naval Surface Warfare Center), Kathleen (Taffy) Kingscott (IBM Research)

3:00-3:30 Break & Networking

3:30-4:15 Proposed Approaches. How do we get there?

Panelists: Asif Bhatti (America's Frontier Fund), Zachary Holman (ASU), Raj Jammy (IMEC), Serge Leef (Microsoft)
4:15-4:45 Break & Networking

4:45-5:30 Where does academic research fit in?
Panelists: Stephen Goodnick (ASU), Clifford King (Analog Devices), Daniel Lopez (Penn State), Gil Vandentop (Intel)

Logistical details:

Date/Time: Wednesday August 9 at 1:30-5:30 pm
Location: MWSCAS 2023 Plenary Hall, Palm Ballroom ABDE, Tempe Mission Palms, 60 E 5th St, Tempe, AZ 85281.
Registration is included with MWSCAS registration for all multi-day registrations and for single day registrations for August 9. There is a separate registration option for the MWSCAS CHIPS Workshop Only. The advance registration fee is $125.
Networking: Breakout rooms will be available for sidebar meetings during the CHIPS Workshop. Please send email to info@mwscas2023.com to reserve a room.

CHIPS Workshop Registration

Alex Liddle
NIST & CHIPS

Michael Fritze
Potomac Institute

Matthew Kay
NSWC Crane

Kathleen Kingscott
IBM Research

Bio for Alex Liddle

J. Alexander Liddle received his B.A. and D. Phil. degrees in Materials Science from the University of Oxford. After his appointment in 1990 as a postdoctoral fellow at Bell Laboratories, he spent the next decade working on the research, development, and eventual commercialization of a novel electron-beam lithography technology. He is currently Chief of the Microsystems and Nanotechnology Division at NIST. His division’s research runs the gamut from quantum nanophotonics to biology. His personal research focus is on nanofabrication and self-assembly for nanomanufacturing. He has published over 275 papers, in areas ranging from electron-beam lithography to DNA-controlled nanoparticle assembly and holds 19 US patents. He is a fellow of the APS and the Washington Academy of Sciences, and a member of the AVS and MRS. He has served on numerous advisory and program evaluation committees, for NSF, DOE, DARPA, and the Semiconductor Research Corporation.

Bio for Michael Fritze

Dr. Michael Fritze
Consultant, TechStrat LLC

Dr. Fritze is an independent technology consultant. He is a Senior Fellow and former Vice President at the Potomac Institute for Policy Studies. He is also a Consultant at Trusted Strategic Solutions His interests include USG trusted microelectronics access strategies, support of needed legacy technologies, DOD innovation policy and outreach to Industry and strengthening the US Microelectronics Industrial Base. He has supported a variety of USG organizations primarily in the DoD on these issues.He is also a member of the Industrial Advisory Committee supporting the NIST CHIPS R&D efforts.

Dr. Fritze was the Director of the Disruptive Electronics Division at the USC Information Sciences Institute. (2010-2015). He also held a Research Professor appointment in the USC Ming Hsieh Department of Electrical Engineering (Electrophysics). His research interests at ISI included Trusted Electronics, CMOS Reliability & Robustness, Low power 3DIC enabled electronics and Rad-hard electronics. He was a Program Manager at the DARPA Microsystems Technology Office (MTO) from 2006-2010. While at DARPA, Dr. Fritze was responsible for Programs in the areas of 3D Integrated Circuits (3DIC), Steep-Subthreshold-slope Transistors (STEEP), Radiation Hardening by Design (RHBD), Carbon Electronics for RF Applications (CERA), Silicon-based RF (TEAM), Ultra-low power Digital (ESE), Highly regular designs (GRATE) and Leading-edge foundry access (LEAP).

Prior to joining DARPA, Dr. Fritze was a staff member from 1995-2006 at MIT Lincoln Laboratory in Lexington, Massachusetts, where he worked on fully-depleted silicon on insulator (FDSOI) technology development with an emphasis on novel devices. Particular interests included highly scaled, tunneling-based, and ultra-low power devices. Dr. Fritze also worked in the area of silicon-based integrated optics. Another research interest at Lincoln Laboratory was in the area of resolution-enhanced optical lithography and nanofabrication with particular emphasis on low volume technological solutions.

Dr. Fritze received a Ph.D. in Physics from Brown University in 1994, working in the area of compound semiconductor quantum well physics. He received a B.S. in Physics in 1984 from Lehigh University. Dr. Fritze is an elected member of Tau Beta Pi and Sigma Xi. He is a recipient of the Office of the Secretary of Defense Medal for Exceptional Public Service awarded in 2010. He is a Senior Member of the IEEE and is active on the GOMAC Conference Program Committee as well as the NDIA Electronics Division Policy Group. Dr. Fritze has published over 75 papers and articles in professional journals and holds several U.S. Patents.

Bio for Matthew Kay

Dr. Matthew J. Kay
Program Manager, Trusted & Assured Microelectronics Program
Distinguished Scientist for Trusted Microelectronics
Naval Surface Warfare Center, Crane Division
Naval Sea Systems Command

Dr. Kay currently provides technical and programmatic oversight as the Program Manager of the Trusted and Assured Microelectronics (T&AM) Program, a multi-billion dollar initiative over the future years defense program that addresses access and assurance of microelectronics for the Department of Defense (DoD). In his over 15 years with the Navy, Dr. Kay has led in numerous roles for the Navy and at the Department level. Dr. Kay has served as the Navy Representative to the Defense Microelectronics Cross-Functional Team, the lead for DoD Unique Needs and the later-Radiation Hardened Technical Execution Area for the T&AM Program, and the Executive Secretariat for the Office of the Under Secretary of Defense for Research and Engineering in support of the Strategic Radiation-Hardened Electronics Council. In April 2023, Dr. Kay was appointed the Distinguished Scientist for Trusted Microelectronics at the Naval Surface Warfare Center in Crane, Indiana.

He has served as a subject matter expert in the area of trusted radiation-hardened microelectronics with a focus on memory technology for various services, agencies, and working groups across the United States Government. Some of the services and agencies he supports and collaborates with include the Navy Strategic Systems Program, Air Force Nuclear Weapons Center, Office of the Deputy Assistant Secretary of Defense for Nuclear Matters, Defense Advanced Research Projects Agency, National Aeronautical and Space Agency, Los Alamos National Labs, Naval Research Lab, as well as T&AM and the Joint Federated Assurance Center, a joint, Department-wide federation of capabilities to support the trusted defense system needs of the Department.

A native of Big Rapids, Michigan, Dr. Kay graduated in 2003 from Wabash College with a bachelor’s degree in Mechanical Engineering. He received his M.S and Ph.D. in Physics from Purdue University’s Physics and Astronomy Department.

Bio for Kathleen (Taffy) Kingscott

Kathleen Kingscott
Senior Strategic Advisor
IBM Research

Kathleen Kingscott is Senior Strategic Advisor in support of IBM Research. She recently retired as Vice President, Strategic Partnerships, IBM Research, where she was responsible for developing collaborative research partnerships between IBM, industry, academia and government. Ms. Kingscott served as IBM’s alternate member of the Semiconductor Industry Association Board of Directors and as chair of the SIA CTO Work Group. She is a member of the Board of Managers of the American Institute of Physics Publishing and chairs the Compensation Committee of the AIPP Board. She is a member of the Innovation Policy Forum of the National Academies of Sciences (NAS) and is currently a committee member of the NAS study, “Global Microelectronics: Models for the Department of Defense in Semiconductor Public-Private Partnerships.” This study will identify, explore, and assess public-private partnership models that have the potential to enable assured access for the production of semiconductors in the United States.

Previously, Kathleen held the IBM Industry Chair at the Industrial College of the Armed Forces, National Defense University, as the first person from industry to join the faculty of the college. While at ICAF her students won the Antonelli Award for the best industry study and the Commandant’s Award for Outstanding Research in Support of the Director, DDRE.

Earlier roles include Director of Worldwide Innovation Policy for the IBM Corporation, responsible for worldwide public policy matters regarding innovation, science and technology. She is a founder and co-chair of the Task Force on American Innovation, a coalition of 60+ organizations which supports federal investment in scientific research. Ms. Kingscott led IBM’s policy work in developing the Trusted Foundry, a partnership between industry and government to develop specialized semiconductors for defense applications. Ms. Kingscott also led IBM’s executive staff participation in the U.S. National Innovation Initiative.

Other prior positions include roles in IBM public policy, Congressional relations, and information technology marketing management. She has also served in numerous industry and association leadership roles, including as a member of the Secretary of Commerce’s Manufacturing Council 2015-2016. Ms. Kingscott retired from IBM with 50 years of service.

Asif Bhatti
America's Frontier Fund

Zachary Holman
ASU

Raj Jammy
IMEC

Serge Leef
Microsoft

Bio for Asif Bhatti

Asif Bhatti is the Director of Strategy & Innovation at America’s Frontier Fund, where he works at the intersection of the science & technology and investment teams and leads investing diligence across numerous portfolios.

A technologist at his core, Asif has spent his career leveraging tech to scale solutions across a number of Fortune 10, fintech, and public/social sectors organizations. Previously, Asif was an Engagement Manager at McKinsey & Company, where he led strategy, technology, and advanced analytics engagements for clients across the public, social, and banking sectors. Prior to this, in 2020, he worked for the Biden-Harris Transition team, leading data and analytics organization for the Strategy & Operations team.

Asif serves on the Chicago Lawyers Committee for Civil Rights NextGen Council. He has been recognized by the Mayor of Chicago for the work he led during COVID-19 for the City of Chicago. He is an advisor for the Tech Talent Project and various civic organizations, and has advised a number of State Gubernatorial Transitions.

Asif earned his B.S. in Biomedical Engineering and Chemistry from the University of Illinois at Urbana-Champaign and M.S. in Data Science and Public Policy from Georgetown University.

Bio for Zachary Holman

Zachary Holman is a Professor in the School of Electrical, Computer, and Energy Engineering at Arizona State University, as well as the Vice Dean for Research and Innovation in the Ira A. Fulton Schools of Engineering. He received his Ph.D. in Mechanical Engineering from the University of Minnesota for his work on plasma-synthesized silicon and germanium nanocrystals, after which he spent two years as a postdoctoral researcher developing high-efficiency silicon solar cells at Ecole Polytechnique Fédérale de Lausanne in Switzerland. His research group at ASU focuses on new semiconductor materials, processes, and device designs. He has been named a Moore Inventor Fellow, Trustees of ASU Professor, Fulton Entrepreneurial Professor, and Joseph C. Palais Distinguished Faculty Scholar, and he is the co-founder of three start-up companies based on ASU research: Swift Coat, Sunflex Solar, and Beyond Silicon.

Bio for Raj Jammy

Dr. Raj Jammy is a semiconductor industry executive and is the President of imec USA operations. He previously served as CTO and Chief Technologist at MITRE Engenuity and Executive Director of the Semiconductor Alliance, which brought together key players across the national semiconductor ecosystem. He led the effort at MITRE Engenuity and the Semiconductor Alliance to develop a vision and an operational plan for the National Semiconductor Technology Center and National Advanced Packaging Manufacturing Program coordinating with DoD Microelectronics interests. From 2016 until recently he was the Global President of Semiconductor Process Control Solutions (PCS) Business Unit at Carl Zeiss with additional responsibility for North America subsidiary of Carl Zeiss Semiconductor BG as President, Carl Zeiss SMT Inc.

Prior to joining Zeiss, Raj was Senior Vice President, Semiconductor and Emerging Technologies Business Unit at Intermolecular, a startup with proprietary combinatorial technologies and software engines. Raj served as the Vice President of Materials and Emerging Technologies at SEMATECH, a global semiconductor industry consortium until 2013, where he worked with companies spanning the industry ecosystem including leading chip makers, suppliers, and universities. He oversaw the consortium's efforts in front-end CMOS logic, novel memory technologies, 3D interconnects, metrology and emerging beyondCMOS technologies. As Chair of SEMATECH Executive Steering Council, he drove decisions on the technical programs, timing and budgets, reporting to the Board of Directors, in coordination with customer company executives. Passionate about technology and building highly motivated teams throughout his career, Raj fostered many collaborative relationships with leading domestic and international companies, startups, universities, global R&D institutions, US and international government agencies.

Raj began his career at IBM working at the renowned IBM Semiconductor Research and Development Center and T.J. Watson Research Labs. He holds more than 50 US patents and is an author/coauthor of over 225 publications/presentations. He has delivered over 35 keynote/invited talks and has contributed to numerous panel discussions. He has served as the General Chair of 2016 IEEE VLSI Technology Symposium and 2015 IEEE Symposium on Technology Systems and Application in VLSI co-organized by ITRI in Taiwan. Currently he serves on the Executive Steering Committee of IEEE VLSI Technology and Circuits Symposium. Raj was appointed to the Department of Commerce Industrial Advisory Committee in October 2022, which provides guidance to the US Secretary of Commerce on a range of issues related to domestic semiconductor research and development in support of the CHIPS for America Act. Raj received a doctorate in Electrical Engineering from Northwestern University.

Bio for Serge Leef

After 4 years of national service at DARPA, Serge Leef joined Microsoft's Azure business in March of 2022 to pursue the vision of cloud based secure microelectronics design, implementation, and fabrication enablement.

At DARPA, Serge was responsible for Secure Silicon, Next Generation Design Tools, and Domestic Microelectronics program portfolio.

Prior to the DARPA appointment, Serge worked at Siemens EDA (formerly Mentor Graphics), where from 2010 until 2018 he was a Vice President of New Ventures, responsible for identifying and developing technology and business opportunities in systems-oriented markets. Additionally, from 1999 to 2018, he served as a division General Manager, responsible for defining strategies and building successful businesses around design automation products in the areas of hardware/software co-design, multi-physics simulation, IP integration, SoC optimization, design data management, automotive/aerospace networking, cloud-based electronic design, Internet of Things (IoT) infrastructure, and hardware cybersecurity.

Prior to joining Mentor, he was responsible for design automation at Silicon Graphics, where he and his team created revolutionary, high-speed simulation tools to enable the design of high-speed 3D graphics chips, which defined the state-of-the-art in visualization, imaging, gaming, and special effects for a decade. Earlier in his career, he managed a CAE/CAD organization at Microchip and developed functional and physical design and verification tools for major 8- and 16-bit microcontroller and microprocessor programs at Intel.

Serge received his Bachelor of Science degree in electrical engineering and Master of Science degree in computer science from Arizona State University. He has served on corporate, state, and academic advisory boards, delivered numerous public speeches, and holds patents in hardware Trojan detection and Internet of Things (loT) infrastructure.

Stephen Goodnick
ASU

Cliff King
Analog Devices

Daniel Lopez
Penn State

Gil Vandentop
Intel

Bio for Stephen Goodnick

Stephen M. Goodnick (M 1987; SM 1990; F 2004) is currently the David and Darleen Ferry Professor of Electrical Engineering at Arizona State University. He received his Ph.D. degrees in electrical engineering from Colorado State University, Fort Collins, in 1983, respectively. He was an Alexander von Humboldt Fellow with the Technical University of Munich, Munich, Germany, and the University of Modena, Modena, Italy, in 1985 and 1986, respectively. He served as Chair and Professor of Electrical Engineering with Arizona State University, Tempe, from 1996 to 2005. He served as Associate Vice President for Research for Arizona State University from 2006-2008, and presently serves as Deputy Director of ASU Lightworks as well as the DOE ULTRA Energy Frontier Research Center. He is also a Hans Fischer Senior Fellow with the Institute for Advanced Studies at the Technical University of Munich. Professionally, he served as President (2012-2013) of the IEEE Nanotechnology Council, and served as President of IEEE Eta Kappa Nu Electrical and Computer Engineering Honor Society Board of Governors, 2011-2012. Some of his main research contributions include analysis of surface roughness at the Si/SiO2 interface, Monte Carlo simulation of ultrafast carrier relaxation in quantum confined systems, global modeling of high frequency and energy conversion devices, full-band simulation of semiconductor devices, transport in nanostructures, and fabrication and characterization of nanoscale semiconductor devices. He has published over 450 journal articles, books, book chapters, and conference proceeding, and is a Fellow of IEEE (2004) and AAAS (2022) for contributions to carrier transport fundamentals and semiconductor devices.

Bio for Cliff King

Cliff King is Sr. Director of External Engagement at Analog Devices in Wilmington, MA. He received his Ph.D. in EE from Stanford Univ. where he fabricated the world’s first SiGe heterojunction bipolar transistor in 1988 using chemical vapor deposition, the dominant technique used today. He was a Distinguished Member of Technical Staff and manager at Bell Laboratories in Murray Hill, NJ where he led a team that developed and placed a high-speed SiGe BiCMOS process in production for optical networking and wireless applications. In 2002, he founded NoblePeak Vision Corp. to produce shortwave infrared cameras using a low dark current Ge-enhanced CMOS image sensor process. He joined L-3 Technologies in 2010 as CTO of the Warrior Systems Division before coming to Analog Devices in 2022. He is a Fellow of the IEEE.

Bio for Daniel Lopez

Daniel Lopez is the Liang Professor of Electrical Engineering at Penn State University and the Director of the Nanofabrication Lab at the Materials Research Institute.

He received his Ph.D. in Physics in 1996 from the Centro Atomico Barilohe in Argentina. Immediately after, he joined IBM T. J. Watson Research Center as a Postdoctoral Fellow, and in 1998, Bell Laboratories (Murray Hill, NJ) as a Research Staff member. At Bell Laboratories, he worked in developing, fabricating, and packaging micro and nano electro-mechanical systems (MEMS and NEMS) for optical communications, imaging, and quantum sensing. In 2000 he received the Bell Labs President's Gold Award, the highest recognition award at Bell Laboratories for developing disruptive technologies directly impacting the business. In 2008, he moved to Argonne National Laboratory to lead the Nanofabrication and Devices group at the Center for Nanoscale Materials. In 2020, after a sabbatical year at NIST (Gaithersburg) working on quantum packaging for atomic sensors, Dr. Lopez joined Penn State University as a named Professor of EE and Director of the Nanofabrication Lab. During the year 2022, he assembled the Mid-Atlantic Semiconductor Hub (MASH), a consortium of 10 universities across six states that combines resources and expertise to meet the need of the semiconductor industry in the U.S. by strengthening and aligning research, manufacturing, and workforce development. He is affiliated with the Microsystems and Nanotechnology Division in the Physical Measurement Lab at the National Institute for Standards and Technologies (NIST) in Gaithersburg, MD.

His research career covered many areas, such as novel materials, micromechanics, optical microsystems, and packaging, but a common theme has been using the interplay among mechanics, photonics, and materials to advance fundamental and applied science.

Bio for Gil Vandentop

Gilroy Vandentop is a VP of Intel Labs and the Director of Corporate University Research. His team manages Intel’s university research investments for key internal technology and business customers. Gilroy is also on the board of the Semiconductor Research Corporation, an industry wide consortium.

Gilroy moved to Intel Labs from TMG’s Components Research group in 2015. While in Components Research, he formed the Novel Materials group and managed Intel’s EUV program through transfer into technology development. From 2000 to 2006, he was responsible for the Packaging Research group in Chandler, AZ. During his first 10 years at Intel, Gilroy worked in Logic Technology Development on silicon process development in the etch and photolithography areas.

Gilroy completed his Ph.D. in physical chemistry at U.C. Berkeley and his B.Sc. in honours chemistry at the University of Alberta.

We are grateful to the IEEE Circuits and Systems Society for their sponsorship of the MWSCAS CHIPS Workshop

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